PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet

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PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet PSoC 62 MCU General Description PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C62x8/A product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals. Features 32-bit Dual CPU Subsystem Segment LCD Drive ■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle ■ Supports up to 101 segments and up to 8 commons multiply, floating point, and memory protection unit (MPU) Serial Communication ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ 13 run-time configurable serial communication blocks (SCBs) 2 ■ User-selectable core logic operation at either 1.1 V or 0.9 V ❐ Eight SCBs: configurable as SPI, I C, or UART ❐ Four SCBs: configurable as I2C or UART ■ Active CPU current slope with 1.1-V core operation ❐ One Deep Sleep SCB: configurable as SPI or I2C ❐ Cortex-M4: 40 µA/MHz ❐ Cortex-M0+: 28 µA/MHz ■ USB Full-Speed device interface ■ Active CPU current slope with 0.9-V core operation ■ Two independent SD Host Controller/eMMC/SD controllers ❐ Cortex-M4: 27 µA/MHz Audio Subsystem ❐ Cortex-M0+: 20 µA/MHz 2 ■ Three DMA controllers ■ Two pulse density modulation (PDM) channels and two I S channels with time division multiplexed (TDM) mode Memory Subsystem Timing and Pulse-Width Modulation ■ 2048-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (Sflash); read-while-write (RWW) ■ Thirty-two timer/counter/pulse-width modulators (TCPWMs) support. Two 8-KB flash caches, one for each CPU. ■ Center-aligned, edge, and pseudo-random modes ■ 1024-KB SRAM with three independent blocks for power and ■ Comparator-based triggering of kill signals data retention control ■ One-time-programmable (OTP) 1-Kb eFuse array Programmable Analog Low-Power 1.7-V to 3.6-V Operation ■ 12-bit 2-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging ■ Six power modes for fine-grained power management ■ Two low-power comparators available in system Deep Sleep ■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention and Hibernate modes ■ On-chip DC-DC buck converter, <1 µA quiescent current ■ Built-in temperature sensor connected to ADC ■ Backup domain with 64 bytes of memory and real-time clock Up to 102 Programmable GPIOs Flexible Clocking Options ■ Two Smart I/O™ ports (16 I/Os) enable Boolean operations on ■ 8-MHz internal main oscillator (IMO) with ±2% accuracy GPIO pins; available during system Deep Sleep ■ Ultra-low-power 32-kHz internal low-speed oscillator (ILO) ■ Programmable drive modes, strengths, and slew rates ■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz) ■ Six overvoltage-tolerant (OVT) pins ■ Two phase-locked loops (PLLs) for multiplying clock Capacitive Sensing frequencies ® ■ Cypress CapSense sigma-delta (CSD) provides best-in-class ■ Frequency-locked loop (FLL) for multiplying IMO frequency signal-to-noise ratio (SNR), liquid tolerance, and proximity ■ Integer and fractional peripheral clock dividers sensing Quad-SPI (QSPI)/Serial Memory Interface (SMIF) ■ Enables dynamic usage of both self and mutual sensing ■ Execute-In-Place (XIP) from external quad SPI flash ■ Automatic hardware tuning (SmartSense™) ■ On-the-fly encryption and decryption ■ 4-KB cache for greater XIP performance with lower power ■ Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-23185 Rev. *Q Revised April 12, 2022

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Security Built into Platform Architecture Profiler ■ ROM-based root of trust via uninterruptible Secured Boot ■ Eight counters provide event or duration monitoring of on-chip ■ Authentication during boot using hardware hashing resources ■ Step-wise authentication of execution images Packages ■ Secured execution of code in execute-only mode for protected routines ■ 128-TQFP, 124-BGA, 100-WLCSP, 68-QFN ■ All debug and test ingress paths can be disabled ■ Up to eight protection contexts Cryptography Accelerator ■ Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions ■ True random number generator (TRNG) function Document Number: 002-23185 Rev. *Q Page 2 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Contents Development Ecosystem ................................................. 4 Analog Peripherals .................................................... 55 PSoC 6 MCU Resources ............................................. 4 Digital Peripherals ..................................................... 61 ModusToolbox Software .............................................. 5 Memory ..................................................................... 64 Blocks and Functionality ................................................. 6 System Resources .................................................... 65 Functional Description..................................................... 8 Ordering Information...................................................... 75 CPU and Memory Subsystem ..................................... 8 PSoC 6 MPN Decoder .............................................. 76 System Resources .................................................... 12 Packaging........................................................................ 77 Programmable Analog Subsystems .......................... 14 Acronyms........................................................................ 82 Programmable Digital ................................................ 16 Document Conventions ................................................. 84 Fixed-Function Digital ................................................ 16 Units of Measure ....................................................... 84 GPIO ......................................................................... 18 Revision History ............................................................. 85 Special-Function Peripherals .................................... 18 Sales, Solutions, and Legal Information ...................... 88 Pinouts ............................................................................ 22 Worldwide Sales and Design Support ....................... 88 Power Supply Considerations....................................... 38 Products .................................................................... 88 Electrical Specifications ................................................ 46 PSoC® Solutions ...................................................... 88 Absolute Maximum Ratings ....................................... 46 Cypress Developer Community ................................. 88 Device-Level Specifications ...................................... 46 Technical Support ..................................................... 88 Document Number: 002-23185 Rev. *Q Page 3 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Development Ecosystem PSoC 6 MCU Resources Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate it into your design. The following is an abbreviated list of resources for PSoC 6 MCU: ■ Overview: PSoC Portfolio, PSoC Roadmap ■ Development Tools ® ■ Product Selectors: PSoC 6 MCU ❐ ModusToolbox software enables cross platform code de- velopment with a robust suite of tools and software libraries ■ Application Notes cover a broad range of topics, from basic ❐ CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit: to advanced level, and include the following: a low-cost hardware platform that enables design and debug AN22174: Getting Started with PSoC 6 MCU of the PSoC 62 CY8C62x8/A product line. It comes with a ❐ CY8CMOD-062-4343W module, industry-leading CapSense ❐ AN218241: PSoC 6 MCU Hardware Design Guide touch buttons and slider, on-board debugger/programmer, ❐ AN213924: PSoC 6 MCU Device Firmware Update Guide microSD card interface, 512-Mb Quad-SPI NOR flash, PDM ❐ AN215656: PSoC 6 MCU Dual-CPU System Design microphone, and a thermistor. It also includes a Murata ❐ AN219528: PSoC 6 MCU Power Reduction Techniques LBEE5KL1DX module, based on the CYW4343W combo AN221111: PSoC 6 MCU Creating a Secured System device. ❐ ❐ CY8CKIT-062S2-43012 PSoC 62S2 Wi-Fi BT Pioneer Kit: a ❐ AN85951: PSoC 4, PSoC 6 MCU CapSense Design Guide low-cost hardware platform that enables design and debug ■ Code Examples demonstrate product features and usage, and of the PSoC 62 MCU and the Murata 1LV Module, based on are also available on Cypress GitHub repositories. the CYW43012 Wi-Fi + Bluetooth combo device. ❐ PSoC 6 CAD libraries provide footprint and schematic sup- ■ Technical Reference Manuals (TRMs) provide detailed port for common tools. BSDL files and IBIS models are also descriptions of PSoC 6 MCU architecture and registers. available. ■ PSoC 6 MCU Programming Specification provides the infor- ■ Training Videos are available on a wide range of topics mation necessary to program PSoC 6 MCU nonvolatile including the PSoC 6 MCU 101 series memory ■ Cypress Developer Community enables connection with fellow PSoC developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC 6 MCU Community Document Number: 002-23185 Rev. *Q Page 4 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet ModusToolbox Software ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is: ■ Comprehensive - it has the resources you need ■ Flexible - you can use the resources in your own workflow ■ Atomic - you can get just the resources you want Cypress provides a large collection of code repositories on GitHub. This includes: ■ Board Support Packages (BSPs) aligned with Cypress kits ■ Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL) ■ Middleware enabling industry-leading features such as CapSense®, Bluetooth Low Energy, and mesh networks ■ An extensive set of thoroughly tested code example applications Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Cypress MCUs. It is a generic interface that can be used across multiple product families. For example, it wraps the PSoC 6 PDL with a simplified API, but the PDL exposes all low-level peripheral functionality. You can leverage the HAL's simpler and more generic interface for most of an application, even if one portion requires finer-grained control. ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox. For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and AN228571: Getting Started with PSoC 6 MCU on ModusToolbox. Figure 1. ModusToolbox Software Tools Document Number: 002-23185 Rev. *Q Page 5 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Blocks and Functionality Figure 2 shows the major subsystems and a simplified view of their interconnections. The color coding shows the lowest power mode where the particular block is still functional (for example, the SRAM is functional down to system Deep Sleep mode). Figure 2. Block Diagram Color Key: PSoC 62 MCU Power Modes and CY8C62x8, CY8C62xA Domains Programmable Analog System LP/ULP Mode System Resources SAR ADC 12 bit CPUs Active/Sleep Power Clocks Temperature OVP LVD IMO ECO Sensor POR BOD FLL 2x PLL System DeepSleep Mode Buck Regulator 2x MCWDT CapSense ILO WDT LCD XRES Reset RTC WCO System Hibernate Mode Backup Regs PMIC Control LP Comparator Backup 32x TCPWM Domain CPU Subsystem SCB Cortex M4F CPU 8x I2C, SPI, 150/50 MHz, 1.1/0.9 V UART, or LIN SWJ, ETM, ITM, CTI 4x I2C, UART, or LIN Cortex M0+ CPU 100/25 MHz, 1.1/0.9 V I2C or SPI SWJ, MTB, CTI Audio Subsystem 3x DMA I2S Controller PDM-PCM Crypto DES/TDES, AES, SHA, Profiler CRC, TRNG, RSA/ECC Accelerator eFuse: 1024 bits QSPI (SMIF) Flash with OTF Encryption/Decryption 2048 KB + 32 KB + 32 KB 8 KB cache for each CPU 2x SD Host Controller SD, SDIO, eMMC SRAM0 512 KB USB USB-FS PHY SRAM1 256 KB SRAM2 256 KB ROM 64 KB Document Number: 002-23185 Rev. *Q Page 6 of 88 System Interconnect (Multi Layer AHB, IPC, MPU/SMPU) Peripheral Interconnect (MMIO, PPU) Peripheral clock (PCLK) SARMUX I/O Subsystem: Up to 102 GPIOs (including 6 OVT), 128-TQFP Package 2x Smart I/O Ports Boundary Scan

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet There are three debug access ports, one each for CM4 and CM0+, and a system port. PSoC 6 MCU devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All device interfaces can be permanently disabled for applications concerned about a reprogrammed device or starting and interrupting flash programming sequences. All programming, debug, and test interfaces can be disabled. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The Eclipse IDE for ModusToolbox provides fully integrated programming and debug support for these devices. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, PSoC 6 provides multiple levels of device security. Document Number: 002-23185 Rev. *Q Page 7 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Functional Description The following sections provide an overview of the features, CPU and Memory Subsystem capabilities and operation of each functional block identified in PSoC 6 has multiple bus masters, as Figure 2 shows. They are: the block diagram in Figure 2. For more detailed information, refer to the following documentation: CPUs, DMA controllers, QSPI, USB, SD Host Controllers, and a Crypto block. Generally, all memory and peripherals can be ■ Board Support Package (BSP) Documentation accessed and shared by all bus masters through multi-layer Arm BSPs are available on GitHub. They are aligned with Cypress AMBA high-performance bus (AHB) arbitration. Accesses kits and provide files for basic device functionality such as between CPUs can be synchronized using an inter-processor communication (IPC) block. hardware configuration files, startup code, and linker files. The BSP also includes other libraries that are required to sup- CPUs port a kit. Each BSP has its own documentation, but typically includes an API reference such as the example here. This There are two Arm Cortex CPUs: search link finds all currently available BSPs on the Cypress The Cortex-M4 (CM4) has single-cycle multiply, a floating-point GitHub site. unit (FPU), and a memory protection unit (MPU). It can run at up to 150 MHz. This is the main CPU, designed for a short interrupt ■ Hardware Abstraction Layer API Reference Manual response time, high code density, and high throughput. The Cypress Hardware Abstraction Layer (HAL) provides a CM4 implements a version of the Thumb instruction set based high-level interface to configure and use hardware blocks on Cypress MCUs. It is a generic interface that can be used on Thumb-2 technology (defined in the Armv7-M Architecture across multiple product families. You can leverage the HAL's Reference Manual). simpler and more generic interface for most of an application, The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU. even if one portion requires finer-grained control. The HAL It can run at up to 100 MHz; however, for CM4 speeds above API Reference provides complete details. Example applica- 100 MHz, CM0+ and bus peripherals are limited to half the speed tions that use the HAL download it automatically from the of CM4. Thus, for CM4 running at 150 MHz, CM0+ and GitHub repository. peripherals are limited to 75 MHz. ■ Peripheral Driver Library (PDL) Application Programming CM0+ is the secondary CPU; it is used to implement system calls Interface (API) Reference Manual and device-level safety and protection features. CM0+ provides a secured, uninterruptible boot function. This helps ensure that The Peripheral Driver Library (PDL) integrates device header post boot, system integrity is checked and memory and files and peripheral drivers into a single package and supports peripheral access privileges are enforced. all PSoC 6 MCU product lines. The drivers abstract the hard- ware functions into a set of easy-to-use APIs. These are fully CM0+ implements the Armv6-M Thumb instruction set (defined documented in the PDL API Reference. Example applications in the Armv6-M Architecture Reference Manual). that use the PSoC 6 PDL download it automatically from the The CPUs have the following power draw, at VDDD = 3.3 V and GitHub repository. using the internal buck regulator: ■ Architecture Technical Reference Manual (TRM) Table 1. Active Current Slope at VDDD = 3.3 V Using the The architecture TRM provides a detailed description of each Internal Buck Regulator resource in the device. This is the next reference to use if it is System Power Mode necessary to understand the operation of the hardware below the software provided by PDL. It describes the architecture ULP LP and functionality of each resource and explains the operation Cortex-M0+ 20 A/MHz 28 A/MHz of each resource in all modes. It provides specific guidance CPU Cortex-M4 27 A/MHz 40 A/MHz regarding the use of associated registers. ■ Register Technical Reference Manual The CPUs can be selectively placed in their Sleep and Deep Sleep power modes as defined by Arm. The register TRM provides a complete list of all registers in the device. It includes the breakdown of all register fields, Both CPUs have nested vectored interrupt controllers (NVIC) for their possible settings, read/write accessibility, and default rapid and deterministic interrupt response, and wakeup interrupt states. All registers that have a reasonable use in typical ap- controllers (WIC) for CPU wakeup from Deep Sleep power plications have functions to access them from within PDL. mode. Note that ModusToolbox and PDL may provide software de- The CPUs have extensive debug support. PSoC 6 has a debug fault conditions for some registers that are different from and access port (DAP) that acts as the interface for device override the hardware defaults. programming and debug. An external programmer or debugger (the “host”) communicates with the DAP through the device serial wire debug (SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP (and subject to restrictions), the host can access the device memory and peripherals as well as the registers in both CPUs. Document Number: 002-23185 Rev. *Q Page 8 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Each CPU offers debug and trace features as follows: of the memory. Each descriptor can transfer data in two nested loops with configurable address increments to the source and ■ CM4 supports six hardware breakpoints and four watchpoints, destination. The size of data transfer per descriptor varies based 4-bit embedded trace macrocell (ETM), serial wire viewer on the type of DMA channel. Refer to the technical reference (SWV), and printf()-style debugging through the single wire manual for detail. output (SWO) pin. CM0+ supports four hardware breakpoints and two watch- Cryptography Accelerator (Crypto) ■ points, and a micro trace buffer (MTB) with 4-KB dedicated This subsystem consists of hardware implementation and RAM. acceleration of cryptographic functions and random number PSoC 6 also has an Embedded Cross Trigger for synchronized generators. debugging and tracing of both CPUs. The Crypto subsystem supports the following: Interrupts ■ Encryption/Decryption Functions This product line has 168 system and peripheral interrupt ❐ Data Encryption Standard (DES) sources, and supports interrupts and system exceptions on both ❐ Triple DES (3DES) CPUs. CM4 has 168 interrupt request lines (IRQ), with the ❐ Advanced Encryption Standard (AES) (128-, 192-, 256-bit) interrupt source ‘n’ directly connected to IRQn. CM0+ has eight ❐ Elliptic Curve Cryptography (ECC) interrupts IRQ[7:0] with configurable mapping of one or more ❐ RSA cryptography functions interrupt sources to any of the IRQ[7:0]. CM0+ also supports eight internal (software only) interrupts. ■ Hashing functions ❐ Secure Hash Algorithm (SHA) Each interrupt supports configurable priority levels (eight levels ❐ SHA-1 for CM4 and four levels for CM0+). Up to four system interrupts can be mapped to each of the CPUs' non-maskable interrupts ❐ SHA-224/-256/-384/-512 (NMI). Up to 39 interrupt sources are capable of waking the ■ Message authentication functions (MAC) device from Deep Sleep power mode using the WIC. Refer to the ❐ Hashed message authentication code (HMAC) technical reference manual for details. ❐ Cipher-based message authentication code (CMAC) InterProcessor Communication (IPC) ■ 32-bit cyclic redundancy code (CRC) generator In addition to the Arm SEV and WFE instructions, a hardware ■ Random number generators InterProcessor Communication (IPC) block is included. It ❐ Pseudo random number generator (PRNG) includes 16 IPC channels and 16 IPC interrupt structures. The ❐ True random number generator (TRNG) IPC channels can be used to implement data communication between the processors. Each IPC channel also implements a Protection Units locking scheme which can be used to manage shared resources. The IPC interrupts let one processor interrupt the other, signaling This product line has multiple types of protection units to control an event. This is used to trigger events such as notify and release erroneous or unauthorized access to memory and peripheral of the corresponding IPC channels. Some IPC channels and registers. CM4 and CM0+ have Arm MPUs for protection at the other resources are reserved, as Table 2 shows: bus master level. Other bus masters use additional MPUs. Shared memory protection units (SMPUs) help implement Table 2. Distribution of IPC Channels and Other Resources protection for memory resources that are shared among multiple Resources Available Resources Consumed bus masters. Peripheral protection units (PPU) are similar to SMPUs but are designed for protecting the peripheral register IPC channels, 8 reserved space. 16 available Protection units support memory and peripheral access IPC interrupts, 8 reserved attributes including address range, read/write, code/data, 16 available privilege level, secured/non-secured, and protection context. Other interrupts 1 reserved Protection units are configured at boot to control access CM0+ NMI Reserved privileges and rights for bus masters and peripherals. Up to eight protection contexts (boot is in protection context 0) allow access Other resources: 1 CM0+ interrupt mux privileges for memory and system resources to be set by the boot clock dividers, DMA process per protection context by bus master and code privilege channels, etc. level. Multiple protection contexts are available. Direct Memory Access (DMA) Controllers This product line has three DMA controllers, which support CPU-independent accesses to memory and peripherals. Two of them have 29 channels each and the third has 4 channels. The descriptors for DMA channels can be in SRAM or flash. Therefore, the number of descriptors is limited only by the size Document Number: 002-23185 Rev. *Q Page 9 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Memory ■ eFuse PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks. A one-time-programmable (OTP) eFuse array consists of 1024 bits, of which 648 are reserved for system use such as ■ Flash die ID, device ID, initial trim settings, device life cycle, and There is up to 2 MB of application flash, organized in 256 KB security settings. The remaining bits are available for storing sectors. key information, hash values, unique IDs or similar custom There are also two 32-KB flash sectors: content. ❐ Auxiliary flash (AUXflash), typically used for EEPROM emu- Each fuse is individually programmed; once programmed (or lation “blown”), its state cannot be changed. Blowing a fuse transi- ❐ Supervisory flash (Sflash). Data stored in Sflash includes de- tions it from the default state of 0 to 1. To program an eFuse, vice trim values, Flash Boot code, and encryption keys. After VDDIO0 must be at 2.5 V ±5%, at 14 mA. the device transitions into the “Secure” lifecycle stage, Sflash can no longer be changed. Because blowing an eFuse is an irreversible process, pro- gramming is recommended only in mass production under The flash has 128-bit-wide accesses to reduce power. Write controlled factory conditions. For more information, see operations can be performed at the row level. A row is PSoC 6 MCU Programming Specifications. 512 bytes. Read operations are supported in both Low Power and Ultra-Low Power modes, however write operations may Boot Code not be performed in Ultra-Low Power mode. Two blocks of code, ROM Boot and Flash Boot, are The flash controller has two caches, one for each CPU. Each pre-programmed into the device and work together to provide cache is 8 KB, with 4-way set associativity. device startup and configuration, basic security features, lifecycle stage management and other system functions. ■ SRAM Up to 1 MB of SRAM is provided in three banks of 512 KB, ■ ROM Boot 256 KB, and 256 KB. Each SRAM bank provides control over On a device reset, the boot code in ROM is the first code to power modes to manage power consumption. For Bank 0 execute. This code performs the following: (512 KB), power control and retention granularity are config- ❐ Integrity checks of flash boot code urable in sixteen 32-KB regions. For banks 1 and 2 (256 KB ❐ Device trim setting (calibration) each) power control is on a per bank basis. For normal oper- ❐ Setting the device protection units ation, the banks can be enabled or disabled to save power. For Deep Sleep mode, the banks can also be configured to ❐ Setting device access restrictions for “Secure” lifecycle states retain data. ROM cannot be changed and acts as the root of trust in a secured system. ■ ROM ■ Flash Boot The 64-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system func- Flash boot is firmware stored in SFlash that ensures that only tions. The ROM contains device initialization, flash write, se- a validated application may run on the device. It also ensures curity, eFuse programming, and other system-level routines. that the firmware image has not been modified, such as by a ROM code is executed only by the CM0+ CPU, in protection malicious third party. context 0. A system function can be initiated by either CPU, Flash boot: or through the DAP. This causes an NMI in CM0+, which ❐ Is validated by ROM Boot causes CM0+ to execute the system function. ❐ Runs after ROM Boot and before the user application ❐ Enables system calls ❐ Configures the Debug Access Port ❐ Launches the user application If the user application cannot be validated, then flash boot ensures that the device is transitioned into a safe state. Document Number: 002-23185 Rev. *Q Page 10 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Memory Map Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided into the Arm-defined regions shown in Table 3. Note that code can be executed from the Code and External RAM regions. Table 3. Address Map for CM4 and CM0+ Address Range Name Use 0x0000 0000 – 0x1FFF FFFF Code Program code region. Data can also be placed here. It includes the exception vector table, which starts at address 0. 0x2000 0000 – 0x3FFF FFFF SRAM Data region. This region is not supported in PSoC 6. 0x4000 0000 – 0x5FFF FFFF Peripheral All peripheral registers. Code cannot be executed from this region. CM4 bit-band in this region is not supported in PSoC 6. 0x6000 0000 – 0x9FFF FFFF External SMIF or Quad SPI, (see the Quad-SPI/Serial Memory Interface RAM (SMIF) section). Code can be executed from this region. 0xA000 0000 – 0xDFFF FFFF External Device Not used. Private 0xE000 0000 – 0xE00F FFFF Peripheral Provides access to peripheral registers within the CPU core. Bus 0xE010 0A000 – 0xFFFF FFFF Device Device-specific system registers. The device memory map shown in Table 4 applies to both CPUs. That is, the CPUs share access to all PSoC 6 MCU memory and peripheral registers. Table 4. Internal Memory Address Map for CM4 and CM0+ Address Range Memory Type Size 0x0000 0000 – 0x0000 FFFF ROM 64 KB 0x0800 0000 – 0x080F FFFF SRAM Up to 1 MB 0x1000 0000 – 0x101F FFFF Application flash Up to 2 MB 0x1400 0000 – 0x1400 7FFF Auxiliary flash, can be used for EEPROM emulation 32 KB 0x1600 0000 – 0x1600 7FFF Supervisory flash 32 KB Note that PSoC 6 SRAM is located in the Arm Code region for both CPUs (see Table 3). There is no physical memory located in the CPUs’ Arm SRAM regions. Document Number: 002-23185 Rev. *Q Page 11 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet System Resources ■ CPU Active – CPU is executing code in system LP or ULP mode Power System ■ CPU Sleep – CPU code execution is halted in system LP or ULP mode The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode ■ CPU Deep Sleep – CPU code execution is halted and system entry (on power-on reset (POR), for example) until voltage levels Deep Sleep is requested in system LP or ULP mode are as required for proper function or generate resets (brown-out detect (BOD)) when the power supply drops below specified ■ System Deep Sleep – Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels (for ■ System Hibernate – Device and I/O states are frozen and the example, below 1.7 V) and the reset occurring. There are no device resets on wakeup voltage sequencing requirements. CPU Active, Sleep, and Deep Sleep are standard Arm-defined The VDDD supply (1.7 to 3.6 V) powers an on-chip buck regulator power modes supported by the Arm CPU instruction set or a low-dropout regulator (LDO), selectable by the user. In architecture (ISA). System LP, ULP, Deep Sleep and Hibernate addition, both the buck and the LDO offer a selectable (0.9 or modes are additional low-power modes supported by PSoC 6 1.1 V) core operating voltage (VCCD). The selection lets users MCU. choose between two system power modes: Clock System ■ System Low Power (LP) operates VCCD at 1.1 V and offers high performance, with no restrictions on device configuration. Figure 3 shows that the clock system of this product line consists of the following: ■ System Ultra Low Power (ULP) operates VCCD at 0.9 V for exceptional low power, but imposes limitations on clock ■ Internal main oscillator (IMO) speeds. ■ Internal low-speed oscillator (ILO) In addition, a backup domain adds an “always on” functionality using a separate power domain supplied by a backup supply ■ Watch crystal oscillator (WCO) (VBACKUP) such as a battery or supercapacitor. It includes a ■ External MHz crystal oscillator (ECO) real-time clock (RTC) with alarm feature, supported by a 32.768-kHz watch crystal oscillator (WCO), and ■ External clock input power-management IC (PMIC) control. Refer to Power Supply ■ Two phase-locked loops (PLLs) Considerations for more details. ■ One frequency-locked loop (FLL) Power Modes Clocks may be buffered and brought out to a pin on a smart I/O PSoC 6 MCU can operate in four system and three CPU power port. modes. These modes are intended to minimize the average power consumption in an application. For more details on power Internal Main Oscillator (IMO) modes and other power-saving configuration options, see the The IMO is the primary source of internal clocking. It is trimmed application note, AN219528: PSoC 6 MCU Low-Power Modes at the factory to achieve the specified accuracy. The IMO and Power Reduction Techniques and the Architecture TRM, frequency is 8 MHz and tolerance is ± 2%. Power Modes chapter. Power modes supported by PSoC 6 MCUs, in order of Internal Low-speed Oscillator (ILO) decreasing power consumption, are: The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can be calibrated against ■ System Low Power (LP) – All peripherals and CPU power modes are available at maximum speed a higher accuracy clock for better accuracy. ■ System Ultra Low Power (ULP) – All peripherals and CPU power modes are available, but with limited speed Document Number: 002-23185 Rev. *Q Page 12 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 3. Clocking Diagram Yellow multiplexers are glitch safe Path Mux (FLL/PLL) Root mux clk_fast Divider CM4 Predivider CLK_HF[0] FLL (1/2/4/8) Peripheral IMO clk_peri Peripheral clocks Divider TCPWM Clock Dividers EXTCLK Predivider CLK_HF[1] clk_slow SCB PLL 0 (1/2/4/8) Audio Divider CM0+ ECO CapSense AHB Predivider CLK_HF[2] QSPI/SMIF, PLL 1 (1/2/4/8) SD Host [1] LCD DMA CLK_PATH3 Analog Predivider CLK_HF[3] eFuse Subsystem USB (1/2/4/8) Smart I/O CLK_PATH4 MMIO Predivider CLK_HF[4] (1/2/4/8) SD Host[0] PPU System LP/ULP Domain System Deep Sleep / Crypto Hibernate Domain Predivider CLK_HF[5] clk_ext (1/2/4/8) ILO CLK_LF WCO External Crystal Oscillators See also Table 6 for additional restrictions for general analog Figure 4 shows all of the external crystal oscillator circuits for this subsystem use. product line. The component values shown are typical; check Table 5. ECO Usage Guidelines ECO Specifications for the crystal values, and the crystal datasheet for the load capacitor values. The ECO and WCO Drive Strength Drive require balanced external load capacitors. For more information, Ports Max Frequency for V ≤ 2.7 V Strength for DDD see the TRM and AN218241, PSoC 6 MCU Hardware Design VDDD ≤ 2.7 V Considerations. Port 11 60 MHz for SMIF DRIVE_SEL 2 DRIVE_SEL 3 (QSPI) Figure 4. Oscillator Circuits Ports 12 and Slow slew rate No restrictions No restrictions 13 setting PSoC 6 Watchdog Timers (WDT, MCWDT) PSoC 6 MCU has one WDT and two multi-counter WDTs (MCWDT). The WDT has a 16-bit free-running counter. Each MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event. The WDT is clocked by the ILO. It can generate interrupt/wakeup MHz XTAL 32.768 kHz XTAL in system LP/ULP, Deep Sleep, and Hibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can generate periodic interrupt / wakeup in system LP/ULP and Deep CL / 2 CL / 2 CL / 2 CL / 2 Sleep power modes. Clock Dividers Integer and fractional clock dividers are provided for peripheral If the ECO is used, note that its performance is affected by GPIO use and timing purposes. There are: switching noise. GPIO ports should be used as Table 5 shows. ■ Eight 8-bit clock dividers ■ Sixteen 16-bit integer clock dividers ■ Four 16.5-bit fractional clock dividers ■ One 24.5-bit fractional clock divider Document Number: 002-23185 Rev. *Q Page 13 of 88 ECO_IN, P12.6 ECO_OUT, P12.7 WCO_IN, P0.0 WCO_OUT, P0.1

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Trigger Routing Programmable Analog Subsystems PSoC 6 MCU contains a trigger multiplexer block. This is a 12-bit SAR ADC collection of digital multiplexers and switches that are used for routing trigger signals between peripheral blocks and between The 12-bit, 2-Msps SAR ADC can operate at a maximum clock GPIOs and peripheral blocks. rate of 36 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. One of three internal There are two types of trigger routing. Trigger multiplexers have reference voltages may be used for an ADC reference voltage. reconfigurability in the source and destination. There are also The references are, V , V /2, and V (nominally 1.2 V and hardwired switches called “one-to-one triggers”, which connect DD DD REF trimmed to ±1%). An external reference may also be used, by a specific source to a destination. The user can enable or disable either driving the VREF pin or routing an external reference to the route. GPIO pin P9.7. These reference options allow ratio-metric readings or absolute readings at the accuracy of the reference Reset used. The input range of the ADC is the full supply voltage PSoC 6 MCU can be reset from a variety of sources: between VSS and VDDA/VDDIOA. The SAR ADC may be ■ Power-on reset (POR) to hold the device in reset while the configured with a mix of single-ended and differential signals in power supply ramps up to the level required for the device to the same configuration. function properly. POR activates automatically at power-up. The SAR ADC’s sample-and-hold (S/H) aperture is ■ Brown-out detect (BOD) reset to monitor the digital voltage programmable to allow sufficient time for signals with a high supply VDDD and generate a reset if VDDD falls below the impedance to settle sufficiently, if required. System performance minimum required logic operating voltage. is 65 dB for true 12-bit precision provided appropriate references ■ External reset dedicated pin (XRES) to reset the device using are used and system noise levels permit it. To improve an external source. The XRES pin is active low. It can be performance in noisy conditions, an external bypass capacitor connected either to a pull-up resistor to V , or to an active for the internal reference amplifier (through the fixed “VREF” DDD drive circuit, as Figure 5 shows. If a pull-up resistor is used, pin), may be added. select its value to minimize current draw when the pin is pulled The SAR is connected to a fixed set of pins through an input low; 4.7 kΩ is typical. multiplexer. The multiplexer cycles through the selected channels autonomously (sequencer scan) and does so with zero Figure 5. XRES Connection Diagram switching overhead (that is, the aggregate sampling bandwidth is equal to 2 Msps whether it is for a single channel or distributed 1.7 to 3.6 V over several channels). The result of each channel is buffered, PSoC 6 so that an interrupt may be triggered only when a full scan of all channels is complete. Also, a pair of range registers can be set VDDD to detect and cause an interrupt if an input exceeds a minimum and/or maximum value. This allows fast detection of out-of-range 4.7 kΩ typ. values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for XRES out-of-range values in software. The SAR can also be XRES drive connected, under firmware control, to most other GPIO pins via the Analog Multiplexer Bus (AMUXBUS). The SAR is not available in system Deep Sleep and Hibernate modes as it ■ Watchdog timer (WDT or MCWDT) to reset the device if requires a high-speed clock (up to 36 MHz). The SAR operating firmware fails to service it within a specified timeout period. range is 1.71 to 3.6 V. ■ Software-initiated reset to reset the device on demand using Temperature Sensor firmware. An on-chip temperature sensor is part of the SAR and may be ■ Logic-protection fault can trigger an interrupt or reset the device scanned by the SAR ADC. It consists of a diode, which is biased if unauthorized operating conditions occur; for example, by a current source that can be disabled to save power. The reaching a debug breakpoint while executing privileged code. temperature sensor may be connected directly to the SAR ADC ■ Hibernate wakeup reset to bring the device out of the system as one of the measurement channels. The ADC digitizes the Hibernate power mode. temperature sensor’s output and a Cypress-supplied software function may be used to convert the reading to temperature Reset events are asynchronous and guarantee reversion to a which includes calibration and linearization. known state. Some of the reset sources are recorded in a register, which is retained through reset and allows software to Low-Power Comparators determine the cause of the reset. Two low-power comparators are provided, which can operate in all power modes. This allows other analog system resources to be disabled while retaining the ability to monitor external voltage levels during system Deep Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator-switch event. Document Number: 002-23185 Rev. *Q Page 14 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Figure 6 shows an overview of the analog subsystem. This diagram is a high-level abstraction. See the TRM for detailed connectivity information. Figure 6. Analog Subsystem AMUXBUSA AMUXBUSB Red dots indicate AMUXBUS splitter P6.0 switches P6.1 LPCOMP0 CSD P1.0 P6.2 inp shield_pad P1.1 P6.3 inn vref_ext P1.2 P6.4 csh P1.3 P6.5 cmod P1.4 P6.6 LPCOMP1 amuxbusa P1.5 P6.7 inp amuxbusb P2.0 inn P2.1 P2.2 P5.0 P2.3 P5.1 P2.4 P5.2 P2.5 P5.3 P2.6 P5.4 P2.7 P5.5 P3.0 P5.6 P3.1 P5.7 P3.2 P3.3 P3.4 P3.5 P4.0 P4.1 P4.2 P4.3 P14.0 P9.7 P14.1 P9.6 P9.5 P9.4 P9.3 P0.0 P9.2 P0.1 P9.1 P0.2 P9.0 P0.3 AREF, 1.2 V P0.4 P0.5 P11.0 P10.0 P10.1 P11.1 P11.2 P10.2 P10.3 P11.3 P11.4 P10.4 P10.5 SAR ADC P11.5 P10.6 vplus P11.6 P10.7 vminus P11.7 vref P12.0 P12.1 VDDA SARREF P12.2 TEMP VDDA / 2 P12.3 temp P12.4 VSS P12.5 To VREF pin, for bypass capacitor P12.6 P12.7 P13.0 P13.1 P13.2 P13.3 P13.4 P13.5 P13.6 P13.7 Document Number: 002-23185 Rev. *Q Page 15 of 88 SARMUX P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet Programmable Digital In this device there are: ■ Eight 32-bit TCPWMs Smart I/O ■ Twenty-four 16-bit TCPWMs Smart I/O is a programmable logic fabric that enables Boolean operations on signals traveling from device internal resources to Serial Communication Blocks (SCB) the GPIO pins or on signals traveling into the device from This product line has 13 SCBs: external sources. A Smart I/O block sits between the GPIO pins 2 and the high-speed I/O matrix (HSIOM) and is dedicated to a ■ Eight can implement either I C, UART, or SPI. single port. Four can implement either I2■ C or UART. There are two Smart I/O blocks: one on Port 8 and one on Port 9. ■ One SCB (SCB #8) can operate in system Deep Sleep mode When Smart I/O is not enabled, all signals on Port 8 and Port 9 with an external clock; this SCB can be either SPI slave or I2C bypass the Smart I/O hardware. slave. Smart I/O supports: I2C Mode: The SCB can implement a full multi-master and slave System Deep Sleep operation interface (it is capable of multimaster arbitration). This block can ■ operate at speeds of up to 1 Mbps (Fast Mode Plus). It also ■ Boolean operations without CPU intervention supports EZI2C, which creates a mailbox address range and ■ Asynchronous or synchronous (clocked) operation effectively reduces I2C communication to reading from and Each Smart I/O block contains a data unit (DU) and eight lookup writing to an array in memory. The SCB supports a 256-byte FIFO for receive and transmit. tables (LUTs). 2 The DU: The I C peripheral is compatible with I2C standard-mode, Fast Mode, and Fast Mode Plus devices as defined in the NXP ■ Performs unique functions based on a selectable opcode. I2C-bus specification and user manual (UM10204). The I2C bus ■ Can source input signals from internal resources, the GPIO I/O is implemented with GPIO in open-drain modes. port, or a value in the DU register. UART Mode: This is a full-feature UART operating at up to Each LUT: 8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all ■ Has three selectable input sources. The input signals may be of which are minor variants of the basic UART protocol. In sourced from another LUT, an internal resource, an external addition, it supports the 9-bit multiprocessor mode that allows the signal from a GPIO pin, or from the DU. addressing of peripherals connected over common Rx and Tx ■ Acts as a programmable Boolean logic table. lines. Common UART functions such as parity error, break Can be synchronous or asynchronous. detect, and frame error are supported. A 256-byte FIFO allows ■ much greater CPU service latencies to be tolerated. Fixed-Function Digital SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used Timer/Counter/Pulse-width Modulator (TCPWM) to synchronize SPI Codecs), and National Microwire (half-duplex ■ The TCPWM supports the following operational modes: form of SPI). The SPI block supports an EZSPI mode in which Timer-counter with compare the data interchange is reduced to reading and writing an array ❐ in memory. The SPI interface operates with a 25-MHz clock. ❐ Timer-counter with capture ❐ Quadrature decoding USB Full-Speed Device Interface ❐ Pulse width modulation (PWM) This product line incorporates a full-speed USB device interface. ❐ Pseudo-random PWM The device can have up to eight endpoints. A 512-byte SRAM ❐ PWM with dead time buffer is provided and DMA is supported. ■ Up, down, and up/down counting modes Note: If the USB pins are not used, connect VDDUSB to ground ■ Clock prescaling (division by 1, 2, 4, ... 64, 128) and leave the P14.0/USBDP and P14.1/USBDM pins unconnected. ■ Double buffering of compare/capture and period values ■ Underflow, overflow, and capture/compare output signals Quad-SPI/Serial Memory Interface (SMIF) ■ Supports interrupt on: A serial memory interface is provided, running at up to 80 MHz. Terminal count – Depends on the mode; typically occurs on It supports single, dual, quad, dual-quad and octal SPI ❐ overflow or underflow configurations, and supports up to four external memory devices. ❐ Capture/compare – The count is captured to the capture reg- It supports two modes of operation: ister or the counter value equals the value in the compare ■ Memory-mapped I/O (MMIO), a command mode interface that register provides data access via registers and FIFOs ■ Complementary output for PWMs ■ Execute in Place (XIP), in which AHB reads and writes are ■ Selectable start, reload, stop, count, and capture event signals directly translated to SPI read and write transfers. for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state. Document Number: 002-23185 Rev. *Q Page 16 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet In XIP mode, the external memory is mapped into the PSoC 6 For eMMC, the supported modes are: MCU internal address space, enabling code execution directly from the external memory. To improve performance, a 4-KB ■ BWC (backward compatibility) cache is included. XIP mode also supports AES-128 on-the-fly ■ SDR encryption and decryption, enabling secured storage and access of code and data in the external memory. Maximum clock restrictions and capacitive loads apply to some modes, and are also dependent on system power mode LCD (LP/ULP). Refer to the SD Host Controller and eMMC Specifications for details. This block drives LCD commons and segments; routing is available to most of the GPIOs. One to eight of the GPIOs must The SD Host Controller complies with the following standards. be used for commons, the rest can be used for segments. Refer to the specifications documents for more information on the protocol and operations. The LCD block has two modes of operation: high speed (8 MHz) and low speed (32 kHz). Both modes operate in system LP and ■ SD Specifications Part 1 Physical Layer Specification Version ULP modes. Low-speed mode operates with reduced contrast in 6.00, supporting card capacities for SDSC (up to 2 GB), SDHC system Deep Sleep mode - review the number of common and (up to 32 GB) and SDXC (up to 2 TB). segment lines, viewing angle requirements, and prototype performance before using this mode. ■ SD Specifications Part A2 SD Host Controller Standard Speci- fication Version 4.20 SD Host Controllers ■ SD Specifications Part E1 SDIO Specifications Version 4.10 This product line contains two Secure Digital (SD) host controllers. They provide communication with IoT connectivity ■ Embedded Multi-Media Card (eMMC) Electrical Standard 5.1 devices such as Bluetooth, Bluetooth Low-Energy and WiFi The SD Host Controller is configured as a master. To be fully radios, as well as combination devices. The controller also compatible with features provided in the driver software for supports embedded MultiMediaCards (eMMC) and Secure speed and efficiency, it supports advanced DMA version 3 Digital (SD) cards. (ADMA3), defined by the SDIO standard, and has a 1-KB Rx/Tx Several bus speed modes under the SD specification are FIFO allowing double buffering of 512-byte blocks. supported: ■ DS (default speed) ■ HS (high speed) ■ SDR12 (single data rate) ■ SDR25 ■ SDR50 ■ DDR50 (double data rate) Document Number: 002-23185 Rev. *Q Page 17 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet GPIO Every pin can generate an interrupt if enabled; each port has an This product line has up to 102 GPIOs, which implement the interrupt request (IRQ) associated with it. following: The port 1 pins are capable of overvoltage-tolerant (OVT) Eight drive strength modes: operation, where the input voltage may be higher than V ■ DDD. OVT pins are commonly used with I2C, to allow powering the ❐ Analog input mode (input and output buffers disabled) chip OFF while maintaining a physical connection to an ❐ Input only operating I2C bus without affecting its functionality. ❐ Weak pull-up with strong pull-down GPIO pins can be ganged to source or sink higher values of ❐ Strong pull-up with weak pull-down current. GPIO pins, including OVT pins, may not be pulled up ❐ Open drain with strong pull-down higher than the absolute maximum; see Electrical Specifications. ❐ Open drain with strong pull-up Strong pull-up with strong pull-down During power-on and reset, the pins are forced to the analog ❐ input drive mode, with input and output buffers disabled, so as ❐ Weak pull-up with weak pull-down not to crowbar any inputs and/or cause excess turn-on current. ■ Input threshold select (CMOS or LVTTL) A multiplexing network known as the high-speed I/O matrix ■ Hold mode for latching previous state (used for retaining the (HSIOM) is used to multiplex between various peripheral and I/O state in system Hibernate mode) analog signals that may connect to an I/O pin. ■ Selectable slew rates for dV/dt-related noise control to improve Analog performance is affected by GPIO switching noise. In EMI order to get the best analog performance, the following The pins are organized in logical entities called ports, which are frequency and drive mode constraints must be applied. The up to 8 pins in width. Data output and pin state registers store, DRIVE_SEL values (refer to Table 6) represent drive strengths respectively, the values to be driven on the pins and the input (see the Architecture and Register TRMs for further detail). states of the pins. See also Table 5 for additional restrictions for ECO use. Table 6. DRIVE_SEL Values Ports Max Frequency Drive Strength for VDDD ≤ 2.7 V Drive Strength for VDDD > 2.7 V Ports 0, 1 8 MHz DRIVE_SEL 2 DRIVE_SEL 3 Port 2 50 MHz DRIVE_SEL 1 DRIVE_SEL 2 Ports 3 to 10 16 MHz; 25 MHz for SPI DRIVE_SEL 2 DRIVE_SEL 3 Ports 11 to 13 80 MHz for SMIF (QSPI). DRIVE_SEL 1 DRIVE_SEL 2 Ports 9 and 10 Slow slew rate setting for TQFP No restrictions No restrictions Packages for ADC performance Special-Function Peripherals The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input stream to Audio Subsystem PCM data output. The following features are supported: This subsystem consists of the following hardware blocks: ■ Programmable data output word length – 16/18/20/24 bits ■ Two Inter-IC Sound (I2S) interfaces ■ Programmable gain amplifier (PGA) for volume control – from ■ Two PDM to PCM decoder channels –12 dB to +10.5 dB in 1.5 dB steps Each of the I2S interfaces implements two independent ■ Configurable PDM clock generation. Range from 384 kHz to hardware FIFO buffers – Tx and Rx, which can operate in master 3.072 MHz or slave mode. The following features are supported: ■ Droop correction and configurable decimation rate for ■ Multiple data formats – I2S, left-justified, Time Division Multi- sampling; up to 48 ksps plexed (TDM) mode A, and TDM mode B ■ Programmable high-pass filter gain ■ Programmable channel/word lengths – 8/16/18/20/24/32 bits ■ Interrupt mask events – not empty, overflow, trigger, underflow ■ Internal/external clock operation up to 192 ksps ■ Configurable FIFO trigger level with DMA support ■ Interrupt mask events – trigger, not empty, full, overflow, underflow, watchdog The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be ■ Configurable FIFO trigger level with DMA support connected to the same PDM Data line. The I2S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones. Document Number: 002-23185 Rev. *Q Page 18 of 88

PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet CapSense Subsystem IDAC CapSense is supported in PSoC 6 MCU through a CapSense The CSD block has two programmable current sources, which sigma-delta (CSD) hardware block. It is designed for offer the following features: high-sensitivity self-capacitance and mutual-capacitance measurements, and is specifically built for user interface ■ 7-bit resolution solutions. ■ Sink and source current modes In addition to CapSense, the CSD hardware block supports three ■ A current source programmable from 37.5 nA to 609 A general-purpose functions. These are available when CapSense is not being used. Alternatively, two or more functions can be ■ Two IDACs that can be used in parallel to form one 8-bit IDAC time-multiplexed in an application under firmware control. The Comparator four functions supported by the CSD hardware block are: The CapSense subsystem comparator operates in the system ■ CapSense Low Power and Ultra-Low Power modes. The inverting input is ■ 10-bit ADC connected to an internal programmable reference voltage and Programmable current sources (IDAC) the non-inverting input can be connected to any GPIO via the ■ AMUXBUS. ■ Comparator CapSense Hardware Subsystem CapSense Figure 7 shows the high-level hardware overview of the Capacitive touch sensors are designed for user interfaces that CapSense subsystem, which includes a delta sigma converter, rely on human body capacitance to detect the presence of a internal clock dividers, a shield driver, and two programmable finger on or near a sensor. Cypress CapSense solutions bring current sources. elegant, reliable, and simple capacitive touch sensing functions to applications including IoT, industrial, automotive, and home The inputs are managed through analog multiplexed buses appliances. (AMUXBUS A/B). The input and output of all functions offered by the CSD block can be provided on any GPIO or on a group of The Cypress-proprietary CapSense technology offers the GPIOs under software control, with the exception of the following features: comparator output and external capacitors that use dedicated ■ Best-in-class signal-to-noise ratio (SNR) and robust sensing GPIOs. under harsh and noisy conditions Self-capacitance is supported by the CSD block using AMUXBUS A, an external modulator capacitor, and a GPIO for ■ Self-capacitance (CSD) and mutual-capacitance (CSX) each sensor. There is a shield electrode (optional) for sensing methods self-capacitance sensing. This is supported using AMUXBUS B ■ Support for various widgets, including buttons, matrix buttons, and an optional external shield tank capacitor (to increase the sliders, touchpads, and proximity sensors drive capability of the shield driver) should this be required. Mutual-capacitance is supported by the CSD block using ■ High-performance sensing across a variety of materials AMUXBUS A, two external integrated capacitors, and a GPIO for Best-in-class liquid tolerance transmit and receive electrodes. ■ The ADC does not require an external component. Any GPIO ■ SmartSense™ auto-tuning technology that helps avoid that can be connected to AMUXBUS A can be an input to the complex manual tuning processes ADC under software control. The ADC can accept VDDA as an ■ Superior immunity against external noise input without needing GPIOs (for applications such as battery voltage measurement). ■ Spread-spectrum clocks for low radiated emissions The two programmable current sources (IDACs) in ■ Gesture and built-in self-test libraries general-purpose mode can be connected to AMUXBUS A or B. They can therefore connect to any GPIO pin. The comparator ■ Ultra-low power consumption resides in the delta-sigma converter. The comparator inverting ■ An integrated graphical CapSense tuner for real-time tuning, input can be connected to the reference. Both comparator inputs testing, and debugging can be connected to any GPIO using AMUXBUS B; see Figure 7. The reference has a direct connection to a dedicated ADC GPIO; see Table 9. The CapSense subsystem slope ADC offers the following The CSD block can operate in active and sleep CPU power features: modes, and seamlessly transition between system LP and ULP ■ Selectable 8- or 10-bit resolution modes. It can be powered down in system Deep Sleep and Hibernate modes. Upon wakeup from Hibernate mode, the CSD ■ Selectable input range: GND to VREF and GND to VDDA on any block requires re-initialization. However, operation can be GPIO input resumed without re-initialization upon exit from Deep Sleep ■ Measurement of VDDA against an internal reference without the mode, under firmware control. use of GPIO or external components Document Number: 002-23185 Rev. *Q Page 19 of 88