XMC4400 Microcontroller Series for Industrial Applications

XMC4400 Microcontroller Series for Industrial Applications XMC4000 Family ARM® Cortex®-M4 32-bit processor core Data Sheet V1.3 2018-09 Microcontrol lers

Edition 2018-09 Published by Infineon Technologies AG 81726 Munich, Germany © 2018 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

XMC4400 Microcontroller Series for Industrial Applications XMC4000 Family ARM® Cortex®-M4 32-bit processor core Data Sheet V1.3 2018-09 Microcontrol lers

XMC4400 XMC4000 Family XMC4400 Data Sheet Revision History: V1.3 2018-09 Previous Versions: V1.2 2015-12 V1.1 2014-03 V1.0 2013-10 V0.6 2012-11 Page Subjects 46 Added RMS Noise parameter in VADC Parameters table. 12 Added a section listing the packages of the different markings. 14 Added BA marking variant. 37 Added footnote explaining minimum VBAT requirements to start the hibernate domain and/or oscillation of a crystal on RTC_XTAL. 38 Changed pull device definition to System Requirement (SR) to reflect that the specified currents are defined by the characteristics of the external load/driver. 38 Added information that PORST Pull-up is identical to the pull-up on standard I/O pins. 45 Updated CAINSW, CAINTOT and RAIN parameters with improved values. 59 Added footnote on test configuration for LPAC measurement. 61 Corrected parameter name of of USB pull device (upstream port receiving) definition according to USB standard (referenced to DM instead of DP) 66 Relaxed RTC_XTAL VPPX parameter value and changed it to a system requirement. 70 Added footnote on current consumption by enabling of fCCU. 71 Added Flash endurance parameter for 64 Kbytes Physical Sector PS4 NEPS4 for devices with BA marking. many Added PG-TQFP-64-19 and PG-LQFP-100-25 package information. 97, 100 Added tables describing the differences between PG-LQFP-100-11 to PG- LQFP-100-25 as well as PG-LQFP-64-19 to PG-TQFP-64-19 packages. 102 Updated to JEDEC standard J-STD-020D for the moisture sensitivity level and added solder temperature parameter according to the same standard. Data Sheet V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Trademarks C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG. ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of ARM, Limited. CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are trademarks of ARM, Limited. Synopsys™ is a trademark of Synopsys, Inc. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Package Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 Digital to Analog Converters (DACx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.5 High Resolution PWM (HRPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.5.1 HRC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.5.2 CMP and 10-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.5.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.6 Low Power Analog Comparator (LPAC) . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.7 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.2.8 USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2.9 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2.10 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.2.11 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Data Sheet 6 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Table of Contents 3.3.4 Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . 77 3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3.8 Embedded Trace Macro Cell (ETM) Timing . . . . . . . . . . . . . . . . . . . . . 83 3.3.9 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.3.9.1 Delta-Sigma Demodulator Digital Interface Timing . . . . . . . . . . . . . . 84 3.3.9.2 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 85 3.3.9.3 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.3.9.4 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.3.10 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.3.11 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 93 3.3.11.1 ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . 93 3.3.11.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . 94 3.3.11.3 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Data Sheet 7 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4500 XMC4000 Family About this Document About this Document This Data Sheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC4500 series devices. The document describes the characteristics of a superset of the XMC4500 series devices. For simplicity, the various device types are referred to by the collective term XMC4500 throughout this manual. XMC4000 Family User Documentation The set of user documentation includes: • Reference Manual – decribes the functionality of the superset of devices. • Data Sheets – list the complete ordering designations, available features and electrical characteristics of derivative devices. • Errata Sheets – list deviations from the specifications given in the related Reference Manual or Data Sheets. Errata Sheets are provided for the superset of devices. Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions of those documents. Data Sheet 8 V1.5, 2017-12 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Summary of Features 1 Summary of Features The XMC4400 devices are members of the XMC4000 Family of microcontrollers based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial Control, Power Conversion, Sense & Control. System System SCU Masters Slaves CPU RTC ARM® CortexTM-M4 ERU0 WDT GPDMA0 Ethernet USB OTG System DCode ICode FCE Bus Matrix Data Code PMU PSRAM DSRAM1 DSRAM2 ROM & Flash USIC0 DSD POSIF1 CCU80 CCU81 HRPWM LEDTS0 CCU43 PORTS DAC PBA0 Peripherals 0 Peripherals 1 PBA1 ERU1 VADC POSIF0 CCU40 CCU41 CCU42 USIC1 CAN Figure 1 XMC4400 System Block Diagram CPU Subsystem • CPU Core – High Performance 32-bit ARM Cortex-M4 CPU – 16-bit and 32-bit Thumb2 instruction set – DSP/MAC instructions – System timer (SysTick) for Operating System support • Floating Point Unit • Memory Protection Unit • Nested Vectored Interrupt Controller • One General Purpose DMA with up-to 8 channels • Event Request Unit (ERU) for programmable processing of external and internal service requests • Flexible CRC Engine (FCE) for multiple bit error detection Data Sheet 9 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Summary of Features On-Chip Memories • 16 KB on-chip boot ROM • 16 KB on-chip high-speed program memory • 32 KB on-chip high speed data memory • 32 KB on-chip high-speed communication memory • 512 KB on-chip Flash Memory with 4 KB instruction cache Communication Peripherals • Ethernet MAC module capable of 10/100 Mbit/s transfer rates • Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY • Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with two nodes, 64 message objects (MO), data rate up to 1MBit/s • Four Universal Serial Interface Channels (USIC), providing four serial channels, usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces • LED and Touch-Sense Controller (LEDTS) for Human-Machine interface Analog Frontend Peripherals • Four Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with input out-of-range comparators • Delta Sigma Demodulator with four channels, digital input stage for A/D signal conversion • Digital-Analog Converter (DAC) with two channels of 12-bit resolution Industrial Control Peripherals • Two Capture/Compare Units 8 (CCU8) for motor control and power conversion • Four Capture/Compare Units 4 (CCU4) for use as general purpose timers • Four High Resoultion PWM (HRPWM) channels • Two Position Interfaces (POSIF) for servo motor positioning • Window Watchdog Timer (WDT) for safety sensitive applications • Die Temperature Sensor (DTS) • Real Time Clock module with alarm support • System Control Unit (SCU) for system configuration and control Input/Output Lines • Programmable port driver control module (PORTS) • Individual bit addressability • Tri-stated in input mode • Push/pull or open drain output mode • Boundary scan test support over JTAG interface Data Sheet 10 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Summary of Features On-Chip Debug Support • Full support for debug features: 8 breakpoints, CoreSight, trace • Various interfaces: ARM-JTAG, SWD, single wire trace 1.1 Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies: • <DDD> the derivatives function set • <Z> the package variant – E: LFBGA – F: LQFP – Q: VQFN • <PPP> package pin count • <T> the temperature range: – F: -40°C to 85°C – K: -40°C to 125°C • <FFFF> the Flash memory size. For ordering codes for the XMC4400 please contact your sales representative or local distributor. This document describes several derivatives of the XMC4400 series, some descriptions may not apply to a specific product. Please see Table 1. For simplicity the term XMC4400 is used for all derivatives throughout this document. 1.2 Device Types These device types are available and can be ordered through Infineon’s direct and/or distribution channels. Table 1 Synopsis of XMC4400 Device Types Derivative1) Package Flash Kbytes SRAM Kbytes XMC4400-F100x512 PG-LQFP-100 512 80 XMC4400-F64x512 PG-yQFP-642) 512 80 XMC4400-F100x256 PG-LQFP-100 256 80 XMC4400-F64x256 PG-yQFP-642) 256 80 XMC4402-F100x256 PG-LQFP-100 256 80 XMC4402-F64x256 PG-yQFP-642) 256 80 1) x is a placeholder for the supported temperature range. 2) y is a placeholder for the QFP package variant, LQFP or TQFP depending on the stepping, see Section 1.3. Data Sheet 11 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Summary of Features 1.3 Package Variants Different markings of the XMC4400 use different package variants. Details of those packages are given in the Package Parameters section of the Data Sheet. Table 2 XMC4400 Package Variants Package Variant Marking Package XMC4400-F100 EES-AA, ES-AA, ES-AB, AB PG-LQFP-100-11 XMC4400-F64 PG-LQFP-64-19 XMC4400-F100 BA PG-LQFP-100-25 XMC4400-F64 PG-TQFP-64-19 1.4 Device Type Features The following table lists the available features per device type. Table 3 Features of XMC4400 Device Types Derivative1) LEDTS Intf. ETH USB USIC MultiCAN Intf. Intf. Chan. Nodes, MO XMC4400-F100x512 1 RMII 1 2 x 2 N0, N1 MO[0..63] XMC4400-F64x512 1 RMII 1 2 x 2 N0, N1 MO[0..63] XMC4400-F100x256 1 RMII 1 2 x 2 N0, N1 MO[0..63] XMC4400-F64x256 1 RMII 1 2 x 2 N0, N1 MO[0..63] XMC4402-F100x256 1 − 1 2 x 2 N0, N1 MO[0..63] XMC4402-F64x256 1 − 1 2 x 2 N0, N1 MO[0..63] 1) x is a placeholder for the supported temperature range. Data Sheet 12 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Summary of Features Table 4 Features of XMC4400 Device Types Derivative1) ADC DSD DAC CCU4 CCU8 POSIF HRPWM Chan. Chan. Chan. Slice Slice Intf. Intf. XMC4400-F100x512 24 4 2 4 x 4 2 x 4 2 1 XMC4400-F64x512 14 4 2 4 x 4 2 x 4 2 1 XMC4400-F100x256 24 4 2 4 x 4 2 x 4 2 1 XMC4400-F64x256 14 4 2 4 x 4 2 x 4 2 1 XMC4402-F100x256 24 4 2 4 x 4 2 x 4 2 1 XMC4402-F64x256 14 4 2 4 x 4 2 x 4 2 1 1) x is a placeholder for the supported temperature range. 1.5 Definition of Feature Variants The XMC4400 types are offered with several memory sizes and number of available VADC channels. Table 5 describes the location of the available Flash memory, Table 6 describes the location of the available SRAMs, Table 7 the available VADC channels. Table 5 Flash Memory Ranges Total Flash Size Cached Range Uncached Range 256 Kbytes 0800 0000H − 0C00 0000H − 0803 FFFFH 0C03 FFFFH 512 Kbytes 0800 0000H − 0C00 0000H − 0807 FFFFH 0C07 FFFFH Table 6 SRAM Memory Ranges Total SRAM Size Program SRAM System Data SRAM Communication Data SRAM 80 Kbytes 1FFF C000H − 2000 0000H − 2000 8000H − 1FFF FFFFH 2000 7FFFH 2000 FFFFH Data Sheet 13 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family Summary of Features Table 7 ADC Channels1) Package VADC G0 VADC G1 VADC G2 VADC G3 PG-LQFP-100 CH0..CH7 CH0..CH7 CH0..CH3 CH0..CH3 PG-LQFP-64 CH0, CH0, CH1, CH0, CH1 CH2, CH3 CH3..CH7 CH3, CH6 1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table. 1.6 Identification Registers The identification registers allow software to identify the marking. Table 8 XMC4400 Identification Registers Register Name Value Marking SCU_IDCHIP 0004 4001H EES-AA, ES-AA SCU_IDCHIP 0004 4002H ES-AB, AB SCU_IDCHIP 0004 4003H BA JTAG IDCODE 101D C083H EES-AA, ES-AA JTAG IDCODE 201D C083H ES-AB, AB JTAG IDCODE 301D C083H BA Data Sheet 14 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family General Device Information 2 General Device Information This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping. 2.1 Logic Symbols VAREF VAGND VDDA VSSA VDDC VDDP VSS (1) (1) (1) (1) (4) (4) (1) VBAT (1) Exp. Die Pad (VSS) RTC_XTAL1 (1) VSSO RTC_XTAL2 Port 0 HIB_IO_0 13 bit HIB_IO_1 Port 1 16 bit XTAL1 XTAL2 Port 2 13 bit USB_DP Port 3 USB_DM 7 bit VBUS Port 4 2 bit Port 14 14 bit Port 5 4 bit Port 15 4 bit PORST TCK JTAG ETM / SWD 3 bit 5 / 1 bit TMS via Port Pins Figure 2 XMC4400 Logic Symbol PG-LQFP-100 Data Sheet 15 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family General Device Information VAREF VAGND VDDA VSSA VDDC VDDP VSS (1) (1) (4) (4) (1) V (1) Exp. Die Pad BAT (VSS) RTC_XTAL1 (1) VSSO RTC_XTAL2 Port 0 HIB_IO_0 12 bit Port 1 9 bit XTAL1 XTAL2 Port 2 10 bit USB_DP USB_DM VBUS Port 14 9 bit PORST TCK JTAG SWD 3 bit 1 bit TMS via Port Pins Figure 3 XMC4400 Logic Symbol PG-LQFP-64 and PG-TQFP-64 Data Sheet 16 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family General Device Information 2.2 Pin Configuration and Definition The following figures summarize all pins, showing their locations on the different packages. P0.1 1 75 P1.4 P0.0 2 74 P1.5 P0.10 3 73 P1.10 P0.9 4 72 P1.11 P3.2 5 71 P1.12 P3.1 6 70 P1.13 P3.0 7 69 P1.14 USB_DM 8 68 P1.15 USB_DP 9 67 TCK VBUS 10 66 TMS VDDP 11 65 PORST VDDC 12 HIB_IO_1 13 XMC4400 64 VDDC 63 VSSO HIB_IO_0 14 62 XTAL2 RTC_XTAL1 15 (Top View) 61 XTAL1 RTC_XTAL2 16 60 VDDP VBAT 17 59 VSS P15.3 18 58 P5.0 P15.2 19 57 P5.1 P14.15 20 56 P5.2 P14.14 21 55 P5.7 P14.13 22 54 P2.6 P14.12 23 53 P2.7 P14.7 24 52 P2.0 P14.6 25 51 P2.1 Figure 4 XMC4400 PG-LQFP-100 Pin Configuration (top view) Data Sheet 17 V1.3, 2018-09 Subject to Agreement on the Use of Product Information P14.5 26 100 P0.2 P14.4 27 99 P0.3 P14.3 28 98 P0.4 P14.2 29 97 P0.5 P14.1 30 96 P0.6 P14.0 31 95 P0.11 VAGND 32 94 P0.12 VAREF 33 93 P3.3 VSSA 34 92 P3.4 VDDA 35 91 P3.5 P14.9 36 90 P3.6 P14.8 37 89 P0.7 P15.9 38 88 P0.8 P15.8 39 87 VDDP P2.15 40 86 VDDC P2.14 41 85 P4.0 VDDC 42 84 P4.1 VDDP 43 83 P1.6 P2.10 44 82 P1.7 P2.9 45 81 P1.8 P2.8 46 80 P1.9 P2.5 47 79 P1.0 P2.4 48 78 P1.1 P2.3 49 77 P1.2 P2.2 50 76 P1.3

XMC4400 XMC4000 Family General Device Information P0.1 1 48 P1.4 P0.0 2 47 P1.5 P0.10 3 46 P1.15 P0.9 4 45 TCK USB_DM 5 44 TMS USB_DP 6 43 PORST VBUS 7 42 VDDC VDDP 8 XMC4400 41 VSSO VDDC 9 40 XTAL2 HIB_IO_0 10 (Top View) 39 XTAL1 RTC_XTAL1 11 38 VDDP RTC_XTAL2 12 37 VSS VBAT 13 36 P2.6 P14.14 14 35 P2.7 P14.7 15 34 P2.0 P14.6 16 33 P2.1 Figure 5 XMC4400 PG-LQFP-64 and PG-TQFP-64 Pin Configuration (top view) Data Sheet 18 V1.3, 2018-09 Subject to Agreement on the Use of Product Information P14.5 17 64 P0.2 P14.4 18 63 P0.3 P14.3 19 62 P0.4 P14.0 20 61 P0.5 VAGND 21 60 P0.6 VAREF 22 59 P0.11 P14.9 23 58 P0.7 P14.8 24 57 P0.8 VDDC 25 56 VDDP VDDP 26 55 VDDC P2.9 27 54 P1.8 P2.8 28 53 P1.9 P2.5 29 52 P1.0 P2.4 30 51 P1.1 P2.3 31 50 P1.2 P2.2 32 49 P1.3

XMC4400 XMC4000 Family General Device Information 2.2.1 Package Pin Summary The following general scheme is used to describe each pin: Table 9 Package Pin Mapping Description Function Package A Package B ... Pad Notes Type Name N Ax ... A2 The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the dedicated pins (i.e. PORST) and supply pins. The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package. The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad, In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about the pad properties are defined in the Electrical Parameters. In the “Notes”, special information to the respective pin/function is given, i.e. deviations from the default configuration after reset. Per default the regular Port pins are configured as direct input with no internal pull device active. Table 10 Package Pin Mapping Function LQFP-100 LQFP-64 Pad Type Notes TQFP-64 P0.0 2 2 A1+ P0.1 1 1 A1+ P0.2 100 64 A2 P0.3 99 63 A2 P0.4 98 62 A2 P0.5 97 61 A2 P0.6 96 60 A2 P0.7 89 58 A2 After a system reset, via HWSEL this pin selects the DB.TDI function. P0.8 88 57 A2 After a system reset, via HWSEL this pin selects the DB.TRST function, with a weak pull-down active. P0.9 4 4 A2 P0.10 3 3 A1+ Data Sheet 19 V1.3, 2018-09 Subject to Agreement on the Use of Product Information

XMC4400 XMC4000 Family General Device Information Table 10 Package Pin Mapping (cont’d) Function LQFP-100 LQFP-64 Pad Type Notes TQFP-64 P0.11 95 59 A1+ P0.12 94 - A1+ P1.0 79 52 A1+ P1.1 78 51 A1+ P1.2 77 50 A2 P1.3 76 49 A2 P1.4 75 48 A1+ P1.5 74 47 A1+ P1.6 83 - A2 P1.7 82 - A2 P1.8 81 54 A2 P1.9 80 53 A2 P1.10 73 - A1+ P1.11 72 - A1+ P1.12 71 - A2 P1.13 70 - A2 P1.14 69 - A2 P1.15 68 46 A2 P2.0 52 34 A2 P2.1 51 33 A2 After a system reset, via HWSEL this pin selects the DB.TDO function. P2.2 50 32 A2 P2.3 49 31 A2 P2.4 48 30 A2 P2.5 47 29 A2 P2.6 54 36 A1+ P2.7 53 35 A1+ P2.8 46 28 A2 P2.9 45 27 A2 P2.10 44 - A2 P2.14 41 - A2 P2.15 40 - A2 Data Sheet 20 V1.3, 2018-09 Subject to Agreement on the Use of Product Information